1. Field of the Invention
The present invention relates to minimizing the runtime code present in the Random Access Memory (RAM), and more specifically to minimizing the runtime code necessary to support a communication standard such as the Universal Serial Bus (USB).
2. Description of the Related Art
Computers are becoming increasingly important in many aspects of life, including homes and businesses. As computers become more important, more advances in computer capabilities are discovered. One such advance was the creation of the Universal Serial Bus (USB). The USB, a serial bus standard, is a communications architecture that allows Personal Computer (PC) users the ability to connect multiple peripherals through a single port while also providing digital telephony capabilities. The USB was designed as an alternative to the legacy PS/2 and RS-232 standards. The USB, a simple two-wire serial communications link, operates at 12 megabits per second (Mbps) and offers both asynchronous and isochronous data transfer. The USB protocols automatically configure a device at startup or when a device is implemented as hot "Plug and Play", that is the device is connected/disconnected or plugged in at run time. Devices such as keyboards, mice, and printers can be connected via the USB. Communication on the USB is bi-directional, with downstream communication toward the device and upstream communication toward the PC.
USB legacy mode support allows a USB keyboard or mouse to transparently replace a PS/2 keyboard or mouse to achieve a high level of compatibility. The USB legacy mode support uses hardware emulation to achieve this compatibility. USB legacy mode support requires a compatible USB host controller. The host controller routes data from the USB devices to the legacy interface, such as a keyboard controller.
USB code is generally contained in the Basic Input/Output System (BIOS) code stored in the BIOS Read Only Memory (ROM). The BIOS code contains the system programs, which interface between the hardware and applications software. After startup, the BIOS code is copied or "shadowed" to a system Random Access Memory (RAM) for quicker and easier access by the computer system. Most RAM access speeds are at least three times as fast as ROM access speeds. To shadow a ROM into a RAM, software is generally used to copy the data from the ROM into the RAM. A memory controller then maps the RAM address space to the ROM address space. This allows the RAM and ROM to occupy the same physical address so that no address alteration routines are necessary. Once shadowed, a BIOS call to a specific ROM address accesses the RAM address, but the RAM address possesses the same data as the ROM. Once the BIOS code is shadowed to the system RAM, the compressed BIOS code is decompressed if necessary.
The BIOS code can be separated in two categories: initialization code and runtime code. Initialization code is executed when the system is initialized at startup and can be implemented to configure a device or a section of the system. Runtime code is executed by the computer system after startup, upon demand, when that specific program in necessary to the operation of the computer system. Because of the limited size of the system RAM and the desirability of leaving space in the system RAM for execution of software applications, the computer system typically removes the initialization code from the system RAM after the initialization code has been executed, thus leaving only runtime code.
Certain microprocessors, such as the Pentium.RTM. processor from Intel Corporation, have included a system management mode (SMM), which is entered upon receipt of a system management interrupt (SMI). SMM code, including initialization and runtime code, can be contained in the BIOS ROM, shadowed to a secure memory space, and decompressed. Originally, SMIs were power management interrupts devised by Intel Corporation for portable systems. Portable computers often draw power from batteries which provide a limited amount of energy. To maximize battery life, an SMI is typically asserted to turn off or reduce the power to any system component not in use. Although originally meant for laptop computers, SMIs have become popular for desktop and other stationary computers as well.
SMIs are asserted by an SMI timer, by a system request, or by other means. Briefly, an SMI is a non-maskable interrupt having almost the highest priority in the system. Only the reset signal R/S* and cache flush signal FLUSH*, which can be conceptualized as interrupts, have a higher priority than the SMI. When an SMI is asserted, a microprocessor maps a portion of memory referred to as the system management mode memory ("SMM memory") into the main memory space. The entire system state is then saved in the SMM memory in a stack-like, last in/first out fashion. After the initial system state is saved, the processor begins executing an SMI handler routine, which is an interrupt service routine to perform specific system management tasks such as reducing power to specific devices. While the routine is executed, other interrupt requests are not serviced, and are ignored until the interrupt routine is completed or the system is reset. When the SMI handler completes its task, the system state is retrieved from the SMM memory, and the main program continues. An SMI active signal referred to as the SMIACT* signal is provided by the processor to indicate operation in SMM.
As mentioned, following assertion of its SMI input (this is generally an active low signal), the processor calls the SMI handler, which addresses an address space that is separate from ordinary main memory. Thereafter, all memory accesses refer only to SMM memory. Input/output ("I/O") accesses via instructions such as IN or OUT are still directed to the normal I/O address space, however. One advantageous side-effect of the hardwired separate address SMM area is that the routines stored in this space cannot be snooped by the cache.
In a typical system management mode implementation, it is intended that battery-buffered SRAM chips be mapped into the address space between 30000h and 3ffffh by default. External hardware can use the SMIACT* signal as a chip select signal and thereby address either the SRAM chips (the SMIACT* signal is at a logic low level), or the normal main memory (the SMIACT* signal is at a logic high level). By using the SMIACT* signal, then, SMM memory and normal memory can be strictly separated.
Certain microprocessors are more flexible than earlier processors in that the SMI handler starting address and the location of the SMM memory space can be changed by the user. Under the Pentium.RTM. design for example, the SMI starting address stored in the microprocessor register is initially set to the conventional 30000h value. Consequently, when the first SMI is asserted, the SMI handler starts at address 38000h (the entry point is offset from the SMM memory base). While the SMI handler routine is executing, however, it may provide a different area of memory to be used as the SMM memory. This new SMM memory may start at any location in the main memory space chosen by the programmer. The SMM memory is a 64 or 128 Kbyte block beginning at the new SMM memory start address. When the SMI handler finishes, the new starting address replaces the old starting address in the microprocessor's SMI starting address register.
When the next SMI is asserted, the microprocessor maps the new 64 or 128 Kbyte block of memory into the main memory space as the SMM memory, and starts the SMI handler at the new starting address at the midpoint of the new SMM memory. For example, during the first SMI service routine, the programmer may change the SMM memory starting point from 030000h to B00000h. When the SMI is next asserted, the microprocessor maps the SMM memory into main memory space between B00000h and B0FFFFh. The microprocessor then references address B08000h for the SMI handler. This feature thus allows the programmer to choose a more convenient location in the main memory.
One implementation of an SMI is to trigger execution of the USB runtime code. A computer system can be implemented so that an SMI is generated at a periodic rate by a USB device. The SMI triggers the execution of the USB code contained in the RAM. The SMI event gives control to the SMI handler and the computer system then enters the SMM. The SMI handler determines if the SMI is an USB SMI. If the SMI is an USB SMI, then the computer system books a call on the USB runtime code contained in the BIOS code shadowed in the RAM. This code is executed, then the SMI handler regains control to address any other SMIs. When all SMIs have been addressed, the SMI handler relinquishes control and SMM is exited. This process is repeated at a fixed period to accommodate the USB devices, such as a keyboard. Therefore, any increase in speed of handling SMIs may result in an overall increase in the speed of the computer system.